The present invention relates to a method of operating NAND flash memory chips, and more particularly, to a method operating a plurality of NAND flash memory chips stacked in a package.
A flash memory is a kind of a non-volatile memory in which data can be stored even when power is off. The flash memory can be electrically programmed and erased and does not need a refresh function by rewriting data at periodical cycles. The term “program” refers to an operation of writing data into memory cells and the term “erase” refers to an operation of erasing data from memory cells.
The flash memory device are generally classified into either NOR flash or NAND flash depending on the structure of the cells and operation conditions. The NOR flash memory has the source of each memory connected to a ground terminal (VSS) and can program and erase with respect to any particular address. The NOR flash memory is mainly used for application fields requiring high-speed operation.
To the contrary, the NAND flash memory has a plurality of memory cells connected in series to form a string. Memory cells connected to a single word line forms one page. The NAND flash memory is mainly used for application fields high data capacity.
The flash memory chips employs a memory controller located between the flash memory and a host system for exchanging data with the host system. The memory controller manages exchange data between flash memory chips stacked in a package and the host system.
FIG. 1 shows NAND flash memory chips F1 through F4 stacked in a package. FIG. 2a is a timing diagram for programming data into the NAND flash memory chips F1 and F2. In FIG. 2a, “IOx” indicates an input signal and “R/Bb” indicates a program start signal. FIG. 2b is a flowchart illustrating a conventional method of programming data into the NAND flash memory chips F1 and F2.
In the related art, a memory controller (not shown) selects and drives one NAND flash memory chip at a time when driving the NAND flash memory chips F1 through F4 shown in FIG. 1. Therefore, when driving two or more NAND flash memory chips (e.g., F1 and F2), a subsequent NAND flash memory chip is driven after the prior NAND flash memory chip has finished a program command, as shown in FIG. 2b. 
Hereinafter, a conventional method of programming data into two NAND flash memory chips stacked in a package will be described with reference to FIG. 2b. 
A program command & an address are applied to the first NAND flash memory chip F1 to drive the NAND flash memory chip F1 at step S11. The program time is then checked at step S12 to determine whether the program operation has been completed at step S13. As a result of the determination, if the program operation has not been completed, the process returns to step S12 wherein the program time is checked after waiting for the program operation to finish.
If it is determined that the program operation has been completed, a program command & an address is applied to a second NAND flash memory chip F2 to drive the second NAND flash memory chip F2 at step S14. The program time is then checked at step S15 to determine whether the program operation has been completed at step S16. As a result of the determination, the process returns to step S15 wherein the program time is checked after waiting for the program operation to finish.
If it is determined that the program operation has been completed, the whole program operation on the NAND flash memory chips F1 and F2 is completed.
That is, in the related art, when driving two or more NAND flash memory chips stacked within a package, the next NAND flash memory chip is driven after the operation of a NAND flash memory chip is finished.
In this conventional method, after a NAND flash memory chip performs the program operation, the next NAND flash memory chip performs the program operation. Therefore, a lot of program (erase or read) time is taken up.